Referring to FIG. 1, a mixed-signal IC chip 11 combines both analogue 15 and digital 14 circuits on a single semiconductor die. Mixed-signal ICs 11 may operate from a single voltage supply 13 (herein referred to as RFVDD) typically of 3 volts (V), with analogue circuits 15 generally powered directly from this voltage. However, a lower supply voltage is also required to power the digital circuits 14 on the chip 11. Thus, an on-chip voltage regulator 18 is often included to generate for example 1.8V (or DIGVDD) from the 3V voltage supply 13 in order to supply lower voltage to the digital circuits 14.
One purpose of the digital circuitry 14 is to control the state of the various analogue circuits 15 on the chip 11 by storing “power down” control bits in digital registers (also referred to as power down register 16). The power down control bits may operate in a “NOT” logic convention. In that case, if the power down bit for a power down circuit 17 in the analogue circuit is set to 0V or logic “LOW’, the circuit will be active and is not powered down; and if the power down bit is set to DIGVDD or logic “HIGH”, the circuit will be powered down.
The power down bits within the power down registers 16 are set by an external digital controller 12, which writes the required values into the registers 16 via an appropriate serial interface 19, such as a Serial Peripheral Interface (SPI) or an Inter-Integrated Circuit (I2C). For the various analogue circuits 15 operating directly from RFVDD, a power down signal at a logic level of DIGVDD may not be sufficient to correctly implement the power down function. Hence, level shift circuits 100 are used to convert DIGVDD power down signals to RFVDD. A typical level shift circuit 100 is shown in FIG. 2. In FIG. 2, the digital inverter INVI 103 generates the inverse of the power down signal PD2V 101 which drives the differential level-shifting latch LVL1 104 to generate PD3V 102. The advantage of using a differential level shift circuit such as that shown in FIG. 2, as opposed to a single-ended level shift amplifier, is that the circuit of FIG. 2 consumes zero d.c. bias current while a single-ended level shift typically requires a d.c. bias current. This additional d.c. bias current may be disadvantageous in portable applications which operate from a battery.
If the functionality of the chip 11 is not required, then the external controller 12 sends an appropriate command via the serial interface 19 to set all the digital bits in the power down registers 16 to HIGH. All the circuits on the chip will be powered off, thus saving power and consequently extending the battery life.
At the same time, problems may also occur if the external controller 12 sends a command to power off the on-chip voltage regulator 18 which generates the digital supply voltage, DIGVDD. Firstly, the digital bits in the power down registers 16 will collapse to zero and the power down level shifter 100 will no longer operate correctly (both power down and its inverse in FIG. 2 fall to zero). The 3V logic power down levels are undefined (tri-state) and may go LOW such that the analogue circuits 15 operating from the RFVDD are powered up drawing significant currents. Secondly, since the digital supply voltage is removed, the serial interface 19 will no longer work and it will not be possible to power up the chip 11 again by sending commands via this interface 19.
One possible solution provided by the present invention is to control the power up and down of the regulator 18 from an external pin rather than via the serial interface 19. This may overcome the second problem of not being able to power the chip 11 again, but may also result in the power down register 16 values going LOW again. In addition, in system-on-chip designs, external pins are typically limited and there may not be one pin spare to implement this regulator power down function. If the regulator power down function is not provided, then in standby mode the regulators generating the digital supply voltage will remain on, which will result in wasted power.